A GALS ASIC implementation from a CAL dataflow description

Summary, in English

This paper presents low power hardware generation, based on a CAL actor language dataflow implementation. The CAL language gives a higher level of abstraction and generate both hardware and software description. The original CAL flow is targeted for hardware-software co-design of complex systems on FPGA. Modifications are done to the original CAL flow to facilitate low power ASIC implementations. The hardware-software co-design and Globally Asynchronous Locally Synchronous (GALS) design at a higher level of abstraction provides more freedom for design-space exploration and reduced design time. Performance is evaluated by a reference design, Orthogonal Frequency-Division Multiplexing (OFDM) multi-standard channel estimator based on robust Minimum Mean-Square Error (MMSE) algorithm. Higher throughput is attained due to inherent parallelism in CAL dataflow and reduced design time for GALS implementation.

• Författare: Hemanth Prabhu; Sherine Thomas; Joachim Rodrigues; Thomas Olsson; Anders Carlsson
• Avdelning/ar: Institutionen för elektro- och informationsteknik; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publiceringsår: 2011
• Språk: Engelska
• Publikation/Tidskrift/Serie: IEEE
• Länkar: http://dx.doi.org/10.1109/NORCHP.2011.6126740
• Dokumenttyp: Konferensbidrag
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Nyckelord: Channel estimation; Clocks; Hardware; OFDM; Software; Synchronization; Throughput
• Conference name: 29th Norchip conference, 2011
• Conference date: 2011-11-14 - 2011-11-15
• Conference place: Lund, Sweden
• Status: Published
• ISBN/ISSN/Övrigt: ISBN: 978-1-4577-0514-4