Sizing of Dual-VT Gates for Sub-VT circuits

In English This paper presents a new design topology, where transistors with
different threshold options are used to design a gate for subthreshold
(sub-VT) operation . Furthermore forced stacking is applied to for
balancing and leakage reduction for circuits operated in the sub-VT
regime. Simulations conducted in 65 nm CMOS show 80% of speed
enhancement with guaranteed functionality (reliability) with no area
overhead.