A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency

Summary, in English

Abstract — The proposed time-to-digital converter (TDC) arranges two Vernier gated-ring-oscillator (GRO) branches in a 2-dimension (2-D) fashion. All delay differences between X-axis phases and Y-axis phases (based on 2-D definition) can be used, rather than only the diagonal line. The large latency time inherited from Vernier structure is therefore dramatically reduced. The TDC is implemented in a 90nm CMOS process and consumes 1.8mA from 1.2V. The measured input range can safely cover a full period of a 50MHz sampling signal. With the same delay elements, the latency time is less than 1/6 of that needed in a standard Vernier TDC.

• Författare: Ping Lu; Pietro Andreani; Antonio Liscidini
• Avdelning/ar: Institutionen för elektro- och informationsteknik; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publiceringsår: 2013
• Språk: Engelska
• Sidor: 195-206
• Publikation/Tidskrift/Serie: Analog Integrated Circuits and Signal Processing
• Volym: 76
• Issue: 2
• Länkar: http://link.springer.com/article/10.1007/s10470-013-0084-0; http://dx.doi.org/10.1007/s10470-013-0084-0
• Dokumenttyp: Artikel i tidskrift
• Förlag: Springer
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Nyckelord: GRO; Vernier; Time to digital converter; 2-D
• Status: Published
• ISBN/ISSN/Övrigt: ISSN: 0925-1030