Portable digital clock generator for digital signal processing applications
Författare
Summary, in English
A fully integrated clock generator with behaviour similar to a PLL is proposed. A free-running ring oscillator is used as internal clock and the output clock is generated using two counters. The clock generator is described in synthesisable VHDL-code and can therefore easily be made from standard cells found in any commercial standard CMOS cell library.
Publiceringsår
2003
Språk
Engelska
Sidor
1372-1374
Publikation/Tidskrift/Serie
Electronics Letters
Volym
39
Issue
19
Dokumenttyp
Artikel i tidskrift
Förlag
IEE
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published
Forskningsgrupp
- Elektronikkonstruktion
ISBN/ISSN/Övrigt
- ISSN: 1350-911X