A Technique for Test Infrastructure Design and Test Scheduling
Publikation/Tidskrift/Serie: [Host publication title missing]
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
We propose a technique for test scheduling and design of test bus infrastructure where test application time and test bus length and width are minimized while constraints on power consumption and test resources are considered. Our approach is suitable for repeated use in the design space exploration process due to its low computational cost. For the final design, we use simulated annealing to optimize the solution. Our technique has been implemented and experimental results show the efficiency of our approach.
- Electrical Engineering, Electronic Engineering, Information Engineering
- simulated annealing
- test scheduling
- test bus infrastructure
Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS