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A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter

Författare:
Publiceringsår: 2012
Språk: Engelska
Sidor: 2593-2596
Publikation/Tidskrift/Serie: [Host publication title missing]
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.

Sammanfattning

This paper presents the design of a digital PLL which uses a high resolution Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter (TDC) for low noise RF application. The TDC uses two gated ring oscillators (GRO) acting as the delay lines in an improved Vernier TDC. The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. Additionally, an automatic tuning bank controller selects the active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The equivalent in-band phase noise at 2.7GHz is -110dBc/Hz with a reference clock of 25MHz. The digital PLL is simulated in a 90nm CMOS process, indicating a current consumption of 21mA from a 1.2V supply.

Nyckelord

  • Electrical Engineering, Electronic Engineering, Information Engineering

Övriga

IEEE International Symposium on Circuits and Systems (ISCAS), 2012
Published
  • ISSN: 0271-4310
  • ISSN: 2158-1525

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