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A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback

Publiceringsår: 2013
Språk: Engelska
Sidor: 47-57
Publikation/Tidskrift/Serie: Analog Integrated Circuits and Signal Processing
Volym: 74
Nummer: 1
Dokumenttyp: Artikel
Förlag: Springer


This paper presents a wireless receiver frontend
intended for cellular applications implemented in a
65 nm CMOS technology. The circuit features a low noise
amplifier (LNA), quadrature passive mixers, and a frequency
divider generating 25 % duty cycle quadrature local
oscillator (LO) signals. A complementary common-gate
LNA is used, and to meet the stringent linearity requirements
it employs positive feedback with transistors biased
in the sub-threshold region, resulting in cancellation of the
third order non-linearity. The mixers are also linearized,
using a baseband to LO bootstrap circuit. Measurements of
the front-end show about 3.5 dB improvement in out-ofband
IIP3 at optimum bias of the positive feedback devices
in the LNA, resulting in an out-of-band IIP3 of 10 dBm.
With a frequency range from 0.7 to 3 GHz the receiver
front-end covers most important cellular bands, with an
input return loss above 9 dB and a voltage gain exceeding
16 dB for all bias settings. The circuit consumes 4.38 mA
from a 1.5 V supply.



  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Positive feedback
  • Bootstrap passive mixer
  • Linearized receiver
  • RF
  • CMOS


  • Swedish Foundation for Strategic Research (SSF)
  • EIT_DARE Digitally-Assisted Radio Evolution
  • Analog RF
  • ISSN: 0925-1030

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