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A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter

Författare:
Publiceringsår: 2012
Språk: Engelska
Sidor: 4
Dokumenttyp: Konferensbidrag

Sammanfattning

Two branches of gated ring oscillators (GRO)
act as the delay lines in 2-dimension Vernier
time-to-digital converter (TDC). The proposed
architecture reduces dramatically the inherent latency of
vernier structure. The already small quantization noise of
the standard Vernier TDC is further first-order shaped by
the GRO operation. The TDC has been simulated in 90nm
CMOS technology. Operating from 50MHz reference
frequency, it achieves a resolution better than 2ps
assuming a signal bandwidth of 1.56MHz (OSR=16), for a
minimum current consumption of 1.8mA from 1.2V.

Disputation

Nyckelord

  • Technology and Engineering
  • Digitall PLL
  • TDC
  • GRO
  • 2-dimention

Övriga

NORCHIP
2012-11-12
Danmark
Inpress
Yes
  • Analog RF

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