A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
Författare
Summary, in English
filter, composed of four half band digital (HBD) filters in
65 nm CMOS are presented. Different unfolded architectures are
analyzed and implemented to combat speed degradation. The
architectures are analyzed for throughput and energy efficiency
over several threshold options. Reliability in the sub-VT domain
is analyzed by Monte-Carlo simulations. The simulation results
are validated by measurements and demonstrate that low-power
standard threshold logic (LP-SVT) and different architectural
flavors are suitable for a low-power implementation. Silicon
measurements prove functionality down to 350mV supply, with
a maximum clock frequency of 500 kHz, having an energy
dissipation of 102 fJ/cycle.
Avdelning/ar
Publiceringsår
2012
Språk
Engelska
Publikation/Tidskrift/Serie
19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- energy dissipation
- measurements
- sub-threshold
- half band digital (HBD) filters
- 65 nm CMOS
- and architectures.
Conference name
IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012
Conference date
2012-12-09 - 2012-12-12
Conference place
Seville, Spain
Status
Published
Projekt
- EIT_UPD Wireless Communication for Ultra Portable Devices
Forskningsgrupp
- Digital ASIC
ISBN/ISSN/Övrigt
- ISBN: 978-1-4673-1261-5
- ISBN: 978-1-4673-1261-5