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A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS

Publiceringsår: 2012
Språk: Engelska
Dokumenttyp: Konferensbidrag
Förlag: IEEE International Conference on Electronics, Circuits, and Systems (ICECS)


Measurements of a sub-threshold (sub-VT) decimation
filter, composed of four half band digital (HBD) filters in
65 nm CMOS are presented. Different unfolded architectures are
analyzed and implemented to combat speed degradation. The
architectures are analyzed for throughput and energy efficiency
over several threshold options. Reliability in the sub-VT domain
is analyzed by Monte-Carlo simulations. The simulation results
are validated by measurements and demonstrate that low-power
standard threshold logic (LP-SVT) and different architectural
flavors are suitable for a low-power implementation. Silicon
measurements prove functionality down to 350mV supply, with
a maximum clock frequency of 500 kHz, having an energy
dissipation of 102 fJ/cycle.



  • Electrical Engineering, Electronic Engineering, Information Engineering
  • energy dissipation
  • measurements
  • sub-threshold
  • half band digital (HBD) filters
  • 65 nm CMOS
  • and architectures.


IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
Seville, Spain
  • Swedish Foundation for Strategic Research (SSF)
  • EIT_UPD Wireless Communication for Ultra Portable Devices
  • Digital ASIC

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