A Highly Parallelized MIMO Detector for Vector-Based Reconfigurable Architectures
Författare
Summary, in English
This paper presents a highly parallelized MIMO signal detection algorithm targeting vector-based reconfigurable architectures. The detector achieves high data-level parallelism and near-ML performance by adopting a vector-architecture-friendly technique - parallel node perturbation. To further reduce the computational complexity, imbalanced node and successive partial node expansion schemes in conjunction with sorted QR decomposition are applied. The effectiveness of the proposed algorithm is evaluated by simulations performed on a simplified 4x4 MIMO LTE-A testbed and operation analysis. Compared to the K-Best detector and fixed-complexity sphere decoder (FSD), the number of visited nodes in the proposed algorithm is reduced by 15 and 1.9 times respectively, with less than 1dB performance degradation. Benefiting from the fully deterministic non-iterative dataflow structure, reconfiguration rate is 95% less than that of the K-Best detector and 17% less than the case of FSD.
Avdelning/ar
Publiceringsår
2013
Språk
Engelska
Sidor
3844-3849
Publikation/Tidskrift/Serie
[Host publication title missing]
Fulltext
Länkar
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- MIMO
- signal detection
- vector processor
- data parallelization
Conference name
IEEE Wireless Communications and Networking Conference (WCNC), 2013
Conference date
2013-04-07 - 2013-04-10
Conference place
Shanghai, China
Status
Published
Projekt
- High Performance Embedded Computing
- EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
Forskningsgrupp
- Digital ASIC