Memory Power Management for Java Processors Using Heap Partitioning and Power Gating
Författare
Summary, in English
The technique has been designed and evaluated for JOP, a Java Optimized Processor, and further implemented and verified in a 65nm CMOS technology using STM low-power high Vt (LPHVT) standard cell libraries. Experiments show that our method accurately follows the memory utilization profile in powering on and off banks, achieving at least 50% leakage power reduction. The performance, area and power penalty introduced by the additional hardware are negligible.
Avdelning/ar
Publiceringsår
2016
Språk
Engelska
Publikation/Tidskrift/Serie
The 14th International Workshop on Java Technologies for Real-Time and Embedded Systems
Dokumenttyp
Konferensbidrag
Ämne
- Embedded Systems
Conference name
14th International Workshop on Java Technologies for Real-Time and Embedded Systems - JTRES 2016
Conference date
2016-08-29 - 2016-09-02
Conference place
Lugano, Switzerland
Status
Published