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A High-Speed QR Decomposition Processor for Carrier-Aggregated LTE-A Downlink Systems

In English

Författare

Summary, in English

This paper presents a high-speed QR decomposition (QRD) processor targeting the carrier-aggregated 4 × 4 Long Term Evolution-Advanced (LTE-A) receiver. The processor provides robustness in spatially correlated channels with reduced complexity by using modifications to the Householder transform, such as decomposing-target redefinition and matrix real-valued decomposition. In terms of hardware design, we extensively explore flexibilities in systolic architectures using a high-level synthesis tool to achieve area-power efficiency. In a 65 nm CMOS technology, the processor occupies a core area of 0.77mm2 and produces 72MQRD per second, the highest reported throughput. The power consumed in the proposed processor is 219mW.

Publiceringsår

2013

Språk

Engelska

Dokumenttyp

Konferensbidrag

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

European Conference on Circuit Theory and Design (ECCTD 2013)

Conference date

2013-09-08 - 2013-09-12

Conference place

Dresden, Germany

Status

Published