Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration

Summary, in English

This paper presents a high throughput, low latency soft-output signal detector for a 4×4 64-QAM MIMO system. To achieve high data-level parallelism and accurate soft information, the detector adopts a node perturbation technique to generate a list of candidate vectors around Zero Forcing, ZF, result. Additionally a fast and hardware friendly node enumeration scheme is developed to significantly reduce processing delay. Implemented using a 65nm CMOS technology, the detector occupies 0.58mm2 core area with 290K gates. The peak throughput is 3Gb/s at 500 MHz clock frequency with a latency of 20ns. Energy consumption per detected bit is 33pJ.

• Författare: Stefan Granlund; Liang Liu; Chenxin Zhang; Viktor Öwall
• Avdelning/ar: Institutionen för elektro- och informationsteknik; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publiceringsår: 2013
• Språk: Engelska
• Publikation/Tidskrift/Serie: [Host publication title missing]
• Länkar: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6702034&tag=1; http://dx.doi.org/10.1109/NORCHIP.2013.6702034
• Dokumenttyp: Konferensbidrag
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: NORCHIP Conference, 2013
• Conference date: 2013-11-11 - 2013-11-12
• Conference place: Vilnius, Lithuania
• Status: Published
• Projekt: High Performance Embedded Computing; EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
• Forskningsgrupp: Digital ASIC