Webbläsaren som du använder stöds inte av denna webbplats. Alla versioner av Internet Explorer stöds inte längre, av oss eller Microsoft (läs mer här: * https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Var god och använd en modern webbläsare för att ta del av denna webbplats, som t.ex. nyaste versioner av Edge, Chrome, Firefox eller Safari osv.

A 31.25/125MSps Continuous-Time Delta-Sigma ADC with 64/59dB SNDR in 130nm CMOS

In English

Författare

Summary, in English

A order 3-bit continuous-time (CT) ΔΣ ADC is presented in this paper. The design equations starting from a discrete-time reference modulator to the circuit implementation are given. The non-return to zero (NRZ) DAC pulses have a half clock cycle loopdelay which is corrected by the feedforward (also known as PI) loop delay compensation, and nonlinearities in the DACs are suppressed by data-weighted averaging. The fabricated 130nm design operates at 31.25/125MHz at a power consumption of 6.04/6.32mA from a 1.2V supply, and achieves an SNDR of 64/59dB at an OSR of 32, resulting in an FOM of 5.73/2.67pJ/cony. step.

Publiceringsår

2013

Språk

Engelska

Publikation/Tidskrift/Serie

[Host publication title missing]

Dokumenttyp

Konferensbidrag

Förlag

IEEE - Institute of Electrical and Electronics Engineers Inc.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

NORCHIP Conference, 2013

Conference date

2013-11-11 - 2013-11-12

Conference place

Vilnius, Lithuania

Status

Published

Forskningsgrupp

  • Analog RF
  • Data converters & RF

ISBN/ISSN/Övrigt

  • ISBN: 978-1-4799-1647-4