Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
Författare
Summary, in English
In this paper we have proposed a test cost model for
core-based 3D Stacked ICs (SICs) connected by Through Silicon
Vias (TSVs). Unlike in the case of non-stacked chips, where the
test flow is well defined by applying the same test schedule both
at wafer sort and at package test, the most cost-efficient test
flow for 3D TSV-SICs is yet undefined. Therefore, analysing the
various alternatives of test flow, we present a cost model with
the optimal test flow. In the test flow alternatives, we analyse the
effect of all possible moments of testing for a 3D TSV-SIC, viz.,
wafer sort, intermediate test and package test. For the optimal
test flow, we have performed experiments with various varying
yield and test time parameters, which further support our claim.
core-based 3D Stacked ICs (SICs) connected by Through Silicon
Vias (TSVs). Unlike in the case of non-stacked chips, where the
test flow is well defined by applying the same test schedule both
at wafer sort and at package test, the most cost-efficient test
flow for 3D TSV-SICs is yet undefined. Therefore, analysing the
various alternatives of test flow, we present a cost model with
the optimal test flow. In the test flow alternatives, we analyse the
effect of all possible moments of testing for a 3D TSV-SIC, viz.,
wafer sort, intermediate test and package test. For the optimal
test flow, we have performed experiments with various varying
yield and test time parameters, which further support our claim.
Publiceringsår
2011
Språk
Engelska
Fulltext
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Dokumenttyp
Konferensbidrag
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- DfT (Design for test)
- Test Architecture
- Scan chain
- Wrapper Chain
- Test Scheduling
- Test Time.
- 3D Stacked Integrated Circuit (SIC)
Conference name
Swedish System-on-Chip Conference, SSoCC 2011
Conference date
2011-05-02 - 2011-05-03
Conference place
Varberg, Sweden
Status
Published
Forskningsgrupp
- Digital ASIC