A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
Författare
Summary, in English
The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280 mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power
Publiceringsår
2014
Språk
Engelska
Publikation/Tidskrift/Serie
[Host publication title missing]
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
FTFC
Conference date
2014-05-04 - 2014-05-06
Conference place
Monaco
Status
Published