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Defect Probability-based System-On-Chip Test Scheduling

In English

Författare

Summary, in English

In this paper we address the test scheduling problem for system-on-chip. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test set in order to schedule the test sets so that the expected total test time will be minimized. It supports different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). Several heuristic algorithms have been developed and experiments performed to demonstrate their efficiency.

Publiceringsår

2003

Språk

Engelska

Sidor

25-32

Dokumenttyp

Konferensbidrag

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • system-on-chip
  • testing
  • defect-detection
  • sequential scheduling
  • concurrent scheduling

Conference name

6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems DDECS 03,2003

Conference date

0001-01-02

Status

Published