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A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS

Författare

Summary, in English

Correct estimation of symbol timing, Carrier Frequency

Offset (CFO), and Signal-to-Noise Ratio (SNR) is crucial

in Orthogonal Frequency Division Multiplexing (OFDM) communication.

Typically, high estimation accuracy is desired, but often

comes with increased complexity. Which has a direct repercussion

in energy consumption. In this article, an architecture based on

Sign-Bit estimation with low complexity, and hence low power

dissipation, is presented. The architecture, is capable of estimating

the afore-mentioned parameters in virtually any OFDM

standard. The proof of concept has been fabricated in 65 nm

CMOS technology with low-power high-VT cells. Measurements

performed with supply voltage of 1.2V. resulted in a power

dissipation of 350 μW, 6 times smaller to that of an equivalent

8-bit architecture, and the lowest power density reported in

literature.

Publiceringsår

2015

Språk

Engelska

Publikation/Tidskrift/Serie

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

Dokumenttyp

Konferensbidrag

Förlag

IEEE - Institute of Electrical and Electronics Engineers Inc.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS), 2015

Conference date

2015-05-24 - 2015-05-27

Conference place

Lisbon, Portugal

Status

Published

Forskningsgrupp

  • Digital ASIC

ISBN/ISSN/Övrigt

  • ISBN: 978-1-4799-8391-9