Du är här

Using Jitterbug to Derive Control Loop Timing Requirements

Publiceringsår: 2003
Språk: Engelska
Publikation/Tidskrift/Serie: Proceedings of CERTS'03 – Co-Design of Embedded Real-Time Systems Workshop
Dokumenttyp: Konferensbidrag


Linking scheduling attributes to control performance specifications is a difficult problem. This paper discusses how the MATLAB toolbox Jitterbug can be used to derive timing requirements for control loops from various control performance specifications. The resulting timing requirements include specifications on sampling periods, latencies, and jitter. An overview of the Jitterbug approach is given, and limitations of the tool are pointed out. A control design example is given, and, finally, topics where more research is needed are outlined.



  • Technology and Engineering



Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se


Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen