Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS

Summary, in English

Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-VT region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0μm/0.6μm, the decoder can offer close to maximum coding gain while operating on very low currents when implemented in 65-nm CMOS technology.

• Författare: Reza Meraji; John B Anderson; Henrik Sjöland; Viktor Öwall
• Avdelning/ar: Institutionen för elektro- och informationsteknik; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publiceringsår: 2011
• Språk: Engelska
• Sidor: 1-4
• Publikation/Tidskrift/Serie: [Host publication title missing]
• Länkar: http://dx.doi.org/10.1109/NORCHP.2011.6126698
• Dokumenttyp: Konferensbidrag
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: 29th Norchip conference, 2011
• Conference date: 2011-11-14 - 2011-11-15
• Conference place: Lund, Sweden
• Status: Published
• ISBN/ISSN/Övrigt: ISBN: 978-1-4577-0514-4