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Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores

Publiceringsår: 2006
Språk: Engelska
Sidor: 1286-1290
Publikation/Tidskrift/Serie: IEEE Journal on Very Large Scale Integration (VLSI) Systems
Volym: 14
Nummer: 11
Dokumenttyp: Artikel
Förlag: IEEE-Inst Electrical Electronics Engineers Inc


This paper presents architectures for supporting dynamic
data scaling in pipeline fast Fourier transforms (FFTs), suitable when implementing large size FFTs in applications such as digital video broadcasting and digital holographic imaging. In a pipeline FFT, data is continuously streaming and must, hence, be scaled without stalling the dataflow. We propose a hybrid floating-point scheme with tailored exponent datapath, and a co-optimized architecture between hybrid floating point and block floating point (BFP) to reduce memory requirements for 2-D signal processing. The presented co-optimization generates a higher signal-to-quantization-noise ratio and requires less memory than for
instance convergent BFP. A 2048-point pipeline FFT has been fabricated in a standard-CMOS process from AMI Semiconductor (Lenart and Öwall, 2003), and a field-programmable gate array prototype integrating a 2-D FFT core in a larger design shows that the architecture is suitable for image reconstruction in digital holographic imaging.



  • Electrical Engineering, Electronic Engineering, Information Engineering
  • multiplexing (OFDM)
  • orthogonal frequency-division
  • transform (FFT)
  • hybrid floating point
  • fast Fourier
  • dynamic data scaling
  • digital video broadcasting (DVB)
  • digital holography
  • block floating point (BFP)
  • convergent BFP (CBFP)


©2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
  • ISSN: 1063-8210

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