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Implementation of a Highly Scalable Architecture for Fast Inversion of Triangular Matrices

Publiceringsår: 2003
Språk: Engelska
Sidor: 1137-1140
Dokumenttyp: Konferensbidrag


In this paper, an F'F'GA implementation of a novel and
highly scalable hardware architecture for fast inversion of
triangular matrices is presented. An integral part of
modem signal processing and communications
applications involves manipulation of large matrices.
Therefore, scalable and flexible hardware architectures
are increasingly sought for. In this paper, the traditional
triangular shaped array architecture with n(n+1)/2
communicating processors, with n being the number of
inputs, is mapped to a linear structure with only n
processors, The linear and the triangular shaped
architectures are compared in aspect of area consumption,
latencies, and maximum clocking speed. This paper also
show that the linear array structure avoids drawhacks such
as non-scalability, large area, and large power
consumption. The implementation is based on a
numerically stahle recurrence algorithm, which has
excellent properties for hardware implementation.



  • Electrical Engineering, Electronic Engineering, Information Engineering


IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
Sharjah, United Arab Emirates

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