Custom Silicon Implementation of a Delayless Acoustic Echo Canceller Algorithm

In English This paper presents a hardware implementation of a
high quality acoustic echo canceller for use in handsfree
telecommunication systems. The implementation
is based on an algorithm with no delay in the signal
path, attractive for communication systems where low
delay is crucial. However, a zero delay algorithm has
higher complexity compared to other canceller solutions.
A custom silicon implementation fulfills quality
and realtime operation while sustaining a low power
consumption. The fabricated processor contains two
million transistors, and the core occupies 20 mm2 in a
0.35 pm CMOS process. At 16 MHz clock frequency,
the chip processes 16 bit samples at a rate of 16 kHz,
while consuming 55 mW for uncorrelated input data.