Arithmetic Reduction of the Static Power Consumption in Nanoscale CMOS
The power consumption is becoming a major obstacle in future circuit design. Referring to Moore's law, by adding more functionality in an exponential way, we will also increase the total power consumption in the same pace. VLSI design has traditionally been concerning the dynamic power consumption as the limiting factor in low power system design. Today, when the feature sizes are in the nano-meter scale, the static power consumption is becoming a dominating factor. This paper indicates an arithmetic reduction of the static power consumption down to 20 % by using bit-serial arithmetic instead of bit-parallel.
- Electrical Engineering, Electronic Engineering, Information Engineering
IEEE 13th International Conference on Electronics, Circuits and Systems (ICECS 2006)