Publikationer
A non-feedback multiphase clock generator
Avdelning/ar:
Publiceringsår: 2002
Språk: Engelska
Sidor: 389-392
Publikation/Tidskrift/Serie: 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)
Dokumenttyp: Konferensbidrag
Förlag: IEEE
Sammanfattning
This paper introduces the design of a new multiphase clock generator with no feedback loop. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1.5 GHz
Disputation
Nyckelord
- Technology and Engineering
- no feedback loop
- multiphase clock generator
- single-stage direct interpolation architecture
- 1/4 frequency divider
- 500 MHz to 1.5 GHz
- short-circuit current suppression interpolator
- 0.35 micron
- 3.3 V
- input clock frequency range
- CMOS process
Övrigt
2002 IEEE International Symposium on Circuits and Systems
2002-05-26/2002-05-29
Phoenix-Scottsdale, AZ, USA
Published
Yes
- ISBN: 0-7803-7448-7

