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A non-feedback multiphase clock generator

Publiceringsår: 2002
Språk: Engelska
Sidor: 389-392
Publikation/Tidskrift/Serie: 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)
Dokumenttyp: Konferensbidrag
Förlag: IEEE


This paper introduces the design of a new multiphase clock generator with no feedback loop. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1.5 GHz



  • Technology and Engineering
  • no feedback loop
  • multiphase clock generator
  • single-stage direct interpolation architecture
  • 1/4 frequency divider
  • 500 MHz to 1.5 GHz
  • short-circuit current suppression interpolator
  • 0.35 micron
  • 3.3 V
  • input clock frequency range
  • CMOS process


2002 IEEE International Symposium on Circuits and Systems
Phoenix-Scottsdale, AZ, USA
  • ISBN: 0-7803-7448-7

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