Du är här

Stacking of heterostructures and metallic elements for a submicron resonant tunneling transistor

Författare:
Publiceringsår: 2002
Språk: Engelska
Sidor: 2
Publikation/Tidskrift/Serie: 7th International Conference on Nanometer-Scale Science and Technology and 21st European Conference on Surface Science
Dokumenttyp: Konferensbidrag
Förlag: Lund Univ

Sammanfattning

We have successfully embedded a metal gate in-between two resonant tunneling double barrier heterostructures (RTD), thus realizing a three dimensional resonant tunneling transistor. The gate is placed 30 nm above and 100 below the two RTD's, respectively. The asymmetric gate allows for a unique control of the current-voltage characteristics, not only controlling the peak current but also the peak voltage. We have modeled the transistor with Cadence, a standard simulation package for circuit simulations, achieving good agreement with experimental data

Disputation

Nyckelord

  • Physics and Astronomy
  • circuit simulations
  • peak voltage
  • simulation package
  • stacking
  • peak current
  • heterostructures
  • metallic elements
  • submicron resonant tunneling transistor
  • metal gate
  • resonant tunneling double barrier heterostructures
  • three dimensional resonant tunneling transistor
  • current-voltage characteristics
  • asymmetric gate
  • 30 to 100 nm
  • W-GaAs

Övriga

Proceedings of 7th International Conference on Nanometer-Scale Science and Technology and 21st European Conference on Surface Science (NANO-7/ECOSS-21)
24-28 June 2002
Malmö, Sweden
Published
Yes

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

 

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen