Publikationer
An all-digital PLL clock multiplier
Avdelning/ar:
Publiceringsår: 2002
Språk: Engelska
Sidor: 275-278
Publikation/Tidskrift/Serie: 2002 IEEE Asia-Pacific Conference on ASIC. Proceedings (Cat. No.02EX547)
Dokumenttyp: Konferensbidrag
Förlag: IEEE
Sammanfattning
A fully integrated digital PLL used as a clock multiplying circuit is designed and manufactured. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply voltage, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm2. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system process change simulation
Disputation
Nyckelord
- Technology and Engineering
- CMOS all-digital PLL clock multipliers
- clock multiplying circuits
- off-chip components
- digital standard cell libraries
- process portable IP-blocks
- CMOS process
- PLL supply voltage
- PLL frequency range
- synthesizable VHDL code
- PLL on-chip area
- integrated digital PLL
- 152 to 366 MHz
- 3.0 V
- digital system process change simulation
- 0.35 micron
Övrigt
2002 IEEE Asia-Pacific Conference on ASIC. Proceedings
6-8 Aug. 2002
Taipei, Taiwan
Published
Yes
- Elektronikkonstruktion
- ISBN: 0-7803-7363-4
