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A low-complexity method for distributed clocking on digital ASICs

Författare:
Publiceringsår: 2004
Språk: Engelska
Sidor: 344-347
Publikation/Tidskrift/Serie: Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (IEEE Cat. No.04EX909)
Dokumenttyp: Konferensbidrag
Förlag: IEEE

Sammanfattning

A low-complexity method using synchronous wrappers is proposed to simplify communication between modules using unsynchronized clocks. To test the method, it is implemented together with a divider and an FFT co-processor. The divider with synchronous wrapper and local clock generator, delivering a 500 MHz clock, is synthesized and verified using post-synthesis simulations for a 0.18 μm 1.8 V CMOS technology. A complete description of the wrapper in synthesizable VHDL-code including local a local clock generator makes the method portable between technologies

Disputation

Nyckelord

  • Technology and Engineering
  • local clock generator
  • divider
  • FFT coprocessor
  • unsynchronized clocks
  • digital ASIC
  • synchronous wrappers
  • distributed clocking
  • low-complexity method
  • CMOS technology
  • post-synthesis simulation
  • VHDL-code
  • large SoC
  • 1.8 V

Övrigt

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
4-5 Aug. 2004
Fukuoka, Japan
Published
Yes
  • Elektronikkonstruktion
  • ISBN: 0-7803-8637-X

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