A low-complexity method for distributed clocking on digital ASICs

In English A low-complexity method using synchronous wrappers is proposed to simplify communication between modules using unsynchronized clocks. To test the method, it is implemented together with a divider and an FFT co-processor. The divider with synchronous wrapper and local clock generator, delivering a 500 MHz clock, is synthesized and verified using post-synthesis simulations for a 0.18 μm 1.8 V CMOS technology. A complete description of the wrapper in synthesizable VHDL-code including local a local clock generator makes the method portable between technologies