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Reduced transceiver-delay for OFDM systems

Publiceringsår: 2004
Språk: Engelska
Sidor: 1242-1245
Publikation/Tidskrift/Serie: 2004 IEEE 59th Vehicular Technology Conference. VTC 2004-Spring
Dokumenttyp: Konferensbidrag
Förlag: IEEE

Sammanfattning

In this paper, it is shown that more than half of the data flow buffer, due to a bit reversed FFT output and cyclic prefix in an OFDM transceiver, can be removed. To achieve this, a new pipelined FFT processor is proposed and a cyclic suffix is used instead of the more commonly used cyclic prefix. The FFT processor is used either with a forward or backward data flow, i.e. performing either a decimation in time or a decimation in frequency FFT. However, this approach precludes wordlength optimization in the processor and therefore a semi floating-point arithmetic is used to achieve high signal-to-noise ratio. Total delay through the transceiver is reduced by 25% and for larger transceivers silicon area is reduced by as much as 25%. In addition, the proposed scheme reduces the required amount of memory accesses to insert a cyclic extension, and has the basic properties of a simple interleaver

Disputation

Nyckelord

  • Technology and Engineering
  • silicon area reduction
  • memory accesses reduction
  • cyclic extension insertion
  • semi floating-point arithmetic
  • frequency decimation
  • time decimation
  • backward data flow
  • forward data flow
  • cyclic suffix
  • pipelined FFT processor
  • bit reversed FFT output
  • cyclic prefix
  • interleaver
  • data flow buffer
  • high signal-to-noise ratio
  • transceiver delay reduction
  • OFDM transceiver

Övrigt

2004 IEEE 59th Vehicular Technology Conference. VTC 2004-Spring
17-19 May 2004
Milan, Italy
Published
Yes
  • Elektronikkonstruktion
  • ISBN: 0-7803-8255-2

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