Silent CMOS circuits aiming for system-on-chip

Summary, in English

A silent CMOS circuit architecture is proposed. Different silent CMOS gate solutions are presented and compared to the normal CMOS precharged gate in switching noise level. A silent 16-bit parallel carry-look-ahead adder is demonstrated. Simulation results on the circuits and the post layout of the adder are given, which shows a 10 times reduction in noise level is possible

• Författare: Jiren Yuan
• Avdelning/ar: Institutionen för elektro- och informationsteknik
• Publiceringsår: 2005
• Språk: Engelska
• Sidor: 278-281
• Publikation/Tidskrift/Serie: 2005 6th International Conference on ASIC Proceedings
• Volym: 1
• Länkar: http://dx.doi.org/10.1109/ICASIC.2005.1611304
• Dokumenttyp: Konferensbidrag
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Nyckelord: 16 bit; parallel carry look ahead adder; switching noise; system-on-chip; silent CMOS circuit architecture; noise level reduction
• Conference name: 2005 6th International Conference on ASIC Proceedings
• Conference date: 2005-10-24 - 2005-10-27
• Conference place: Shanghai, China
• Status: Published
• ISBN/ISSN/Övrigt: ISBN: 0780392108; ISBN: 0-7803-9210-8