Javascript verkar inte påslaget? - Vissa delar av Lunds universitets webbplats fungerar inte optimalt utan javascript, kontrollera din webbläsares inställningar.
Du är här

InAs WRAP-gate nanowire transistors

Publiceringsår: 2007
Språk: Engelska
Sidor: 527-529
Publikation/Tidskrift/Serie: Conference Proceedings - International Conference on Indium Phosphide and Related Materials
Dokumenttyp: Konferensbidrag
Förlag: Institute of Electrical and Electronics Engineers Inc., Piscataway, NJ 08855-1331, United States


InAs nanowire wrap-gate transistors have been fabricated in a vertical geometry using matrices of 11×11 nanowires. The fabrication process is based on conventional and scalable technologies that are adopted for the nanowire transistors. A SiNx layer is used as gate dielectric and a wrap-gate of 80 nm gate length is formed. These transistors show good DC characteristics with drive currents above 1 mA and a transconductance of 0.28 mS at Vsd=0.5V. The transistors operate in depletion mode. © 2007 IEEE.



  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Condensed Matter Physics
  • Drive currents
  • Nanowire transistors
  • WRAP-gate nanowire
  • Scalable technologies


IPRM'07: IEEE 19th International Conference on Indium Phosphide and Related Materials
Matsue, Japan
  • ISSN: 1092-8669

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen