Webbläsaren som du använder stöds inte av denna webbplats. Alla versioner av Internet Explorer stöds inte längre, av oss eller Microsoft (läs mer här: * https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Var god och använd en modern webbläsare för att ta del av denna webbplats, som t.ex. nyaste versioner av Edge, Chrome, Firefox eller Safari osv.

InAs WRAP-gate nanowire transistors

Författare

Summary, in English

InAs nanowire wrap-gate transistors have been fabricated in a vertical geometry using matrices of 11×11 nanowires. The fabrication process is based on conventional and scalable technologies that are adopted for the nanowire transistors. A SiN<sub>x</sub> layer is used as gate dielectric and a wrap-gate of 80 nm gate length is formed. These transistors show good DC characteristics with drive currents above 1 mA and a transconductance of 0.28 mS at V<sub>sd</sub>=0.5V. The transistors operate in depletion mode. © 2007 IEEE.

Publiceringsår

2007

Språk

Engelska

Sidor

527-529

Publikation/Tidskrift/Serie

Conference Proceedings - International Conference on Indium Phosphide and Related Materials

Dokumenttyp

Konferensbidrag

Förlag

IEEE - Institute of Electrical and Electronics Engineers Inc.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Condensed Matter Physics

Nyckelord

  • Drive currents
  • Nanowire transistors
  • WRAP-gate nanowire
  • Scalable technologies

Conference name

IPRM'07: IEEE 19th International Conference on Indium Phosphide and Related Materials

Conference date

2007-05-14 - 2007-05-18

Conference place

Matsue, Japan

Status

Published

ISBN/ISSN/Övrigt

  • ISSN: 1092-8669
  • CODEN: CPRMEG