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InAs WRAP-gate nanowire transistors

Publiceringsår: 2007
Språk: Engelska
Sidor: 527-529
Publikation/Tidskrift/Serie: Conference Proceedings - International Conference on Indium Phosphide and Related Materials
Dokumenttyp: Konferensbidrag
Förlag: Institute of Electrical and Electronics Engineers Inc., Piscataway, NJ 08855-1331, United States

Sammanfattning

InAs nanowire wrap-gate transistors have been fabricated in a vertical geometry using matrices of 11×11 nanowires. The fabrication process is based on conventional and scalable technologies that are adopted for the nanowire transistors. A SiNx layer is used as gate dielectric and a wrap-gate of 80 nm gate length is formed. These transistors show good DC characteristics with drive currents above 1 mA and a transconductance of 0.28 mS at Vsd=0.5V. The transistors operate in depletion mode. © 2007 IEEE.

Disputation

Nyckelord

  • Technology and Engineering
  • Drive currents
  • Nanowire transistors
  • WRAP-gate nanowire
  • Scalable technologies

Övriga

IPRM'07: IEEE 19th International Conference on Indium Phosphide and Related Materials
2014-05-15
Matsue, Japan
Published
Yes
  • ISSN: 1092-8669
  • CODEN: CPRMEG

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