Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias

Summary, in English

Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.

• Författare: Breeta Sengupta; Urban Ingelsson; Erik Larsson
• Avdelning/ar: Institutionen för elektro- och informationsteknik
• Publiceringsår: 2012
• Språk: Engelska
• Sidor: 442-447
• Publikation/Tidskrift/Serie: [Host publication title missing]
• Fulltext: - 182 kB; Download statistics
• Länkar: http://dx.doi.org/10.1109/VLSID.2012.111
• Dokumenttyp: Konferensbidrag
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Nyckelord: Test Scheduling; 3D stacked IC; JTAG; Test Architecture; Through Silicon Via
• Conference name: 2012 25th International Conference on VLSI Design
• Conference date: 2012-01-07
• Conference place: Hyderbad, India
• Status: Published
• Forskningsgrupp: Digital ASIC