Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster
Författare
Publiceringsår
2011
Språk
Engelska
Publikation/Tidskrift/Serie
European Test Symposium (ETS11), Trondheim, Norway, May 23-27, 2011., 2011
Fulltext
Dokumenttyp
Konferensbidrag
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
IEEE European Test Symposium (ETS), 2011
Conference date
2011-05-23 - 2011-05-27
Conference place
Trondheim, Norway
Status
Published
Forskningsgrupp
- Digital ASIC