Test Planning for Core-based 3D Stacked ICs under Power Constraints
Författare
Summary, in English
Test planning for core-based 3D stacked ICs under power constraint is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D SICs with two chips and 3D SICs with an arbitrary number of chips. We motivate the problem by demostrating the trade-off between test time and hardware, within a power constraint, while arriving at the minimal cost.
Publiceringsår
2012
Språk
Engelska
Fulltext
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Dokumenttyp
Konferensbidrag
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- Test Architecture
- DfT (Design for test)
- Scan chain
- Wrapper Chain
- Test Scheduling
- Test Time.
- 3D Stacked Integrated Circuit (SIC)
Conference name
IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)
Conference date
2012-01-07 - 2012-01-08
Conference place
Hyderabad, India
Status
Published
Forskningsgrupp
- Digital ASIC