Webbläsaren som du använder stöds inte av denna webbplats. Alla versioner av Internet Explorer stöds inte längre, av oss eller Microsoft (läs mer här: * https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Var god och använd en modern webbläsare för att ta del av denna webbplats, som t.ex. nyaste versioner av Edge, Chrome, Firefox eller Safari osv.

A parallel 2Gops/s image convolution processor with low I/O bandwidth

In English

Författare

Summary, in English

A customized image processor for real time convolution of an image has been developed. Image convolution requires an extensive amount of calculation capacity and I/O communication which is hard to sustain with standard processors in real time. Therefore, a customized processor has been designed with a tailored architecture. The processors have a total sustained calculation capacity of >2G arithmetic operations/s at 20 MHz clock frequency, surpassing that of TMS320C80 for this application due to the tailored architecture.

Publiceringsår

1995

Språk

Engelska

Sidor

87-90

Publikation/Tidskrift/Serie

[Host publication title missing]

Dokumenttyp

Konferensbidrag

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

IEEE ASIC Conference and Exhibit

Conference date

1995-09-18 - 1995-09-22

Conference place

Austin, TX, United States

Status

Published

ISBN/ISSN/Övrigt

  • ISSN: 1063-0988
  • ISBN: 0-7803-2707-1