Noise optimization of an inductively degenerated CMOS low noise amplifier

Summary, in English

This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the inductive source degeneration topology. The effects of the gate induced current noise on the noise performance are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of the LNA. As a result, very low noise figures become possible already at very low power consumption levels

• Författare: Pietro Andreani; Henrik Sjöland
• Avdelning/ar: Institutionen för elektro- och informationsteknik
• Publiceringsår: 2001
• Språk: Engelska
• Sidor: 835-841
• Publikation/Tidskrift/Serie: IEEE Transactions on Circuits and Systems - 2, Analog and Digital Signal Processing
• Volym: 48
• Issue: 9
• Länkar: http://ieeexplore.ieee.org/iel5/82/20839/00964996.pdf; http://dx.doi.org/10.1109/82.964996
• Dokumenttyp: Artikel i tidskrift
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• ISBN/ISSN/Övrigt: ISSN: 1057-7130