A hardware efficiency analysis for simplified trellis decoding blocks
Publikation/Tidskrift/Serie: [Host publication title missing]
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.
- Electrical Engineering, Electronic Engineering, Information Engineering
- Trellis decoding blocks
- Computational operations
- Hardware efficiency
IEEE Workshop on Signal Processing Systems - Design and Implementation (SiPS)
- ISSN: 1520-6130
- ISBN: 0-7803-9333-3