A two-stage mm-wave PA with 18.5% PAE in 65 nm CMOS
Författare
Summary, in English
A two-stage mm-wave power amplifier (PA) is presented. Designed in a 65 nm CMOS process, the PA employs capacitive neutralization in each stage for increased differential isolation and gain. Baluns are used for single-ended input/output signal to balanced signal conversion, and the interstage matching consists of a 2:1 transformer. With a 1.2 V supply, at 67 GHz, measurements show a gain of 16.8 dB, a 1dB-compression point (P1dB) of 8.4 dBm and a saturated output power (Psat) of 11.8dBm, with a peak power added efficiency (PAE) of 18.5 %. The PA core occupies an area of 100 um x 300 um.
Avdelning/ar
Publiceringsår
2015
Språk
Engelska
Sidor
1-3
Publikation/Tidskrift/Serie
2015 Asia-Pacific Microwave Conference (APMC)
Volym
1
Dokumenttyp
Konferensbidrag
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
2015 Asia-Pacific Microwave Conference (APMC)
Conference date
2015-12-06 - 2015-12-09
Conference place
Nanjing, China
Status
Published
ISBN/ISSN/Övrigt
- ISBN: 978-1-4799-8765-8