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A low-complexity VLSI architecture for square root MIMO detection

In English

Författare

  • Zhan Guo
  • Peter Nilsson

Summary, in English

Low-complexity VLSI (very large scale integration) architecture of the square root algorithm is proposed for MIMO (multiple-input multiple-output) detection. As a modification to the traditional QR triangular array based architecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade-offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA (field programmable gate arrays). For a 4-transmit and 4-receive antennas MIMO system using QPSK (quarter phase-shift keying) modulation scheme, a detecting throughput of 80 Mb/s can be achieved

Publiceringsår

2003

Språk

Engelska

Sidor

304-309

Publikation/Tidskrift/Serie

Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

Dokumenttyp

Konferensbidrag

Förlag

ACTA Press

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • multiple-input multiple-output
  • square root algorithm
  • power consumption
  • finite word length analysis
  • VirtexE series Xilinx FPGA
  • field programmable gate arrays
  • 4-transmit antennas
  • quarter phase-shift keying
  • 4-receive antennas
  • QPSK modulation
  • MIMO detection
  • VLSI architecture
  • very large scale integration

Conference name

IASTED International Conference on Circuits, Signals and Systems, 2003

Conference date

2003-05-19 - 2003-05-21

Conference place

Cancun, Mexico

Status

Published

Forskningsgrupp

  • Elektronikkonstruktion

ISBN/ISSN/Övrigt

  • ISBN: 0-88986-351-2