An all-digital PLL clock multiplier
Författare
Summary, in English
Publiceringsår
2002
Språk
Engelska
Sidor
275-278
Publikation/Tidskrift/Serie
2002 IEEE Asia-Pacific Conference on ASIC. Proceedings (Cat. No.02EX547)
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- CMOS all-digital PLL clock multipliers
- clock multiplying circuits
- off-chip components
- digital standard cell libraries
- process portable IP-blocks
- CMOS process
- PLL supply voltage
- PLL frequency range
- synthesizable VHDL code
- PLL on-chip area
- integrated digital PLL
- 152 to 366 MHz
- 3.0 V
- digital system process change simulation
- 0.35 micron
Conference name
2002 IEEE Asia-Pacific Conference on ASIC. Proceedings
Conference date
2002-08-06 - 2002-08-08
Conference place
Taipei, Taiwan
Status
Published
Forskningsgrupp
- Elektronikkonstruktion
ISBN/ISSN/Övrigt
- ISBN: 0-7803-7363-4