Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
Författare
Summary, in English
show significant reduction in test cost compared to when using schemes, which are optimized for non-stacked chips.
Publiceringsår
2014
Språk
Engelska
Sidor
1-6
Publikation/Tidskrift/Serie
VLSI Test Symposium (VTS), 2014 IEEE 32nd
Fulltext
Länkar
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- DfT (Design for test)
- Test Architecture
- Scan chain
- Wrapper Chain
- Test Scheduling
- Test Time.
- 3D Stacked Integrated Circuit (SIC)
- Integer Linear Programming (ILP)
Conference name
IEEE VLSI Test Symposium (VTS)
Conference date
2014-04-13 - 2014-04-17
Conference place
Napa, CA, United States
Status
Published
Forskningsgrupp
- Digital ASIC
ISBN/ISSN/Övrigt
- ISSN: 1093-0167