A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing

Summary, in English

This paper presents a 1MHz bandwidth, ΔƩ fractional-N PLL as the frequency synthesizer for LTE. A noise cancellation path composed of a novel hybrid ΔƩ DAC with 9 output bits is incorporated into the PLL in order to cancel the out-of-band phase noise caused by the quantization error. Further, a re-timing circuit is proposed to reduce the nonlinearity in the Charge Pump and provide pulse shaping signals to decrease the charge mismatch. Therefore, a wide loop bandwidth can be obtained while keeping reasonable performance of out-of-band phase noise. The proposed synthesizer is simulated in 90nm CMOS process, consuming 20.96mA from a 1 V supply.

• Författare: Dawei Ye; Ping Lu; Pietro Andreani; Ronan van der Zee
• Avdelning/ar: Institutionen för elektro- och informationsteknik; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publiceringsår: 2013
• Språk: Engelska
• Sidor: 169-172
• Publikation/Tidskrift/Serie: [Host publication title missing]
• Länkar: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6571809
• Dokumenttyp: Konferensbidrag
• Förlag: ISCAS
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE International Symposium on Circuits and Systems (ISCAS), 2013
• Conference date: 2013-05-19 - 2013-05-23
• Conference place: Beijing, China
• Status: Published
• ISBN/ISSN/Övrigt: ISSN: 2158-1525; ISSN: 0271-4310