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Two Flavors of 4kb Standard-Cell Based Subvt Memory in 65 nm CMOS

In English

Författare

  • Oskar Andersson
  • Pascal Meinerzhagen
  • Babak Mohammadi
  • Syed Muhammad Yasser Sherazi
  • Andreas Burg
  • Joachim Rodrigues

Summary, in English

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub- VT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D- latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220mV) and a total energy of 14fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65 nm CMOS reported to date.

Publiceringsår

2013

Språk

Engelska

Dokumenttyp

Konferensbidrag

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

Swedish System-On-Chip Conference (SSoCC), 2013

Conference date

2013-05-06 - 2013-05-07

Conference place

Ystad, Sweden

Status

Published