Modeling of n-InAs metal oxide semiconductor capacitors with high-kappa gate dielectric

Summary, in English

A qualitative analysis on capacitance-voltage and conductance data for high-kappa/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary. (C) 2014 AIP Publishing LLC.

• Författare: Aein Shiri Babadi; Erik Lind; Lars-Erik Wernersson
• Avdelning/ar: Institutionen för elektro- och informationsteknik; NanoLund: Centre for Nanoscience
• Publiceringsår: 2014
• Språk: Engelska
• Publikation/Tidskrift/Serie: Applied Physics Reviews
• Volym: 116
• Issue: 21
• Länkar: http://dx.doi.org/10.1063/1.4903520
• Dokumenttyp: Artikel i tidskrift
• Förlag: American Institute of Physics (AIP)
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• ISBN/ISSN/Övrigt: ISSN: 1931-9401