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Area and power efficient trellis computational blocks in 0.13μm CMOS

In English

Författare

Summary, in English

Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13μm CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption

Publiceringsår

2005

Språk

Engelska

Sidor

344-347

Publikation/Tidskrift/Serie

IEEE International Symposium on Circuits and Systems (ISCAS)

Dokumenttyp

Konferensbidrag

Förlag

IEEE - Institute of Electrical and Electronics Engineers Inc.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • rate 1/2 convolutional codes
  • complementary property
  • trellis-based decoding architectures
  • reduced complexity
  • trellis computational blocks
  • cell area
  • CMOS process
  • branch metric unit
  • add-compare-select unit
  • 0.13 micron
  • power consumption
  • silicon implementation

Conference name

IEEE International Symposium on Circuits and Systems (ISCAS), 2005

Conference date

2005-05-23 - 2005-05-26

Conference place

Kobe, Japan

Status

Published

Forskningsgrupp

  • Elektronikkonstruktion

ISBN/ISSN/Övrigt

  • ISBN: 0-7803-8834-8