FPGA implementation of real-time image convolutions with three level of memory hierarchy
Författare
Summary, in English
Publiceringsår
2003
Språk
Engelska
Sidor
424-427
Publikation/Tidskrift/Serie
[Host publication title missing]
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- field programmable gate arrays
- FPGA implementation
- real time image convolutions
- memory hierarchy exploration
- image convolution processor
- finite state machine
- application specific integrated circuits
- incremental branch optimization
- data transfer
- control system synthesis
- potential power savings
- ASIC implementation
- I/O bandwidth reduction
- clock frequency
- C64x processor
- streamlined data flow
- Xilinx VirtexE FPGA
- pipelined datapath
Conference name
IEEE International Conference on Field-Programmable Technology (FPT)
Conference date
2003-12-15 - 2003-12-17
Conference place
Tokyo, Japan
Status
Published
ISBN/ISSN/Övrigt
- ISBN: 0-7803-8320-6