A low-jitter and low-power frequency synthesizer applied to 1000 Base-T Ethernet

Summary, in English

This paper adopts a high-speed TSPC frequency and phase detector,a typical charge pump,and cross-coupled differential delay cells to realized a good frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Mbps modes.This frequency synthesizer can not only meet the requirements of the transmitter for very precise rising (falling) edge time control but also offer much finer time-interval clocks than VCO natural multi-phase outputs,thus greatly saving area and power.The data show that the σ of the voltage control oscillator jitter_ cycle-cycle is only 11ps while that of the reference clock jitter_ cycle-cycle is 16ps.This indicates that the frequency synthesizer works well for transmitters and receivers.The circuit is designed with SMIC 0.18μm standard CMOS technology,the power supply is 1.8V,and the power is lower than 4mW.

• Författare: Ping Lu; Yan Wang; Liang Li; Junyan Ren
• Publiceringsår: 2006
• Språk: Kinesiska
• Sidor: 137-142
• Publikation/Tidskrift/Serie: Journal of Semiconductors
• Volym: 27
• Issue: 1
• Länkar: http://en.cnki.com.cn/Article_en/CJFDTOTAL-BDTX200601028.htm
• Dokumenttyp: Artikel i tidskrift
• Förlag: IOS Press
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Nyckelord: Ethernet frequency synthesizer clock jitter
• Status: Published
• ISBN/ISSN/Övrigt: ISSN: 1674-4926