InAs WRAP-gate nanowire transistors
Publikation/Tidskrift/Serie: Conference Proceedings - International Conference on Indium Phosphide and Related Materials
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
InAs nanowire wrap-gate transistors have been fabricated in a vertical geometry using matrices of 11×11 nanowires. The fabrication process is based on conventional and scalable technologies that are adopted for the nanowire transistors. A SiNx layer is used as gate dielectric and a wrap-gate of 80 nm gate length is formed. These transistors show good DC characteristics with drive currents above 1 mA and a transconductance of 0.28 mS at Vsd=0.5V. The transistors operate in depletion mode. © 2007 IEEE.
- Electrical Engineering, Electronic Engineering, Information Engineering
- Condensed Matter Physics
- Drive currents
- Nanowire transistors
- WRAP-gate nanowire
- Scalable technologies
IPRM'07: IEEE 19th International Conference on Indium Phosphide and Related Materials
- ISSN: 1092-8669
- CODEN: CPRMEG