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A CMOS power amplifier using ground separation technique

In English

Författare

Summary, in English

This work presents an on-chip ground separation technique for power amplifiers. The ground separation technique is based on separating the grounds of the amplifier stages on the chip and thus any parasitic feedback paths are removed. Simulation and experimental results show that the technique makes the amplifier less sensitive to bondwire inductance, and consequently improves the stability and performance. A two-stage CMOS RF power amplifier for WCDMA mobile phones is designed using the proposed on-chip ground separation technique. The power amplifier is fabricated in a 0.25mum CMOS process. It has a measured 1-dB compression point between 1920MHz and 1980MHz of 21.3plusmn0.5dBm with a maximum PAE of 24%. The amplifier has sufficiently low ACLR for WCDMA (-33 dB) at an output power of 20 dBm

Publiceringsår

2007

Språk

Engelska

Sidor

281-284

Publikation/Tidskrift/Serie

Proceedings of 7th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

Dokumenttyp

Konferensbidrag

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

Conference date

2007-01-10 - 2007-01-12

Status

Published

Forskningsgrupp

  • Elektronikkonstruktion

ISBN/ISSN/Övrigt

  • ISBN: 0-7803-9765-7