Chip for wideband digital predistortion RF power amplifier linearisation
Författare
Summary, in English
The authors present a custom chip for use in digital predistortion linearisation of RF power amplifiers. The chip is mainly implemented with systolic arrays. At maximum clock-rate, 130 MHz, the throughput is 16 Msamples/s with a 5 V supply voltage and power consumption of 1 W. A throughput of 2 Msamples/s is achieved at a 1.2 V supply voltage with 6 mW power consumption
Publiceringsår
1997
Språk
Engelska
Sidor
925-926
Publikation/Tidskrift/Serie
Electronics Letters
Volym
33
Issue
11
Länkar
Dokumenttyp
Artikel i tidskrift
Förlag
IEE
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published
ISBN/ISSN/Övrigt
- ISSN: 1350-911X